verilog

module classDesign2(CLOCK,RESET,ENABLE,DONE,BACK,a,b,c,d,e,f,g);
	input CLOCK,RESET,ENABLE;
	output DONE,BACK,a,b,c,d,e,f,g;
	reg C1=0,C2=0;
	wire DONE,BACK,a,b,c,d,e,f,g;
	reg [2:0] Sreg=3'b000,Snext=3'b001;
	parameter [2:0] S0=3'b000,
					S1=3'b001,
					S2=3'b010,
					S3=3'b011,
					S4=3'b100,
					S5=3'b101,
					S6=3'b110,
					S7=3'b111;
					
	always @(posedge CLOCK)
	begin
		case({RESET,ENABLE})
			2'b10,2'b11:	Sreg<=S0;
			2'b01:			Sreg<=Snext;
			default:		Sreg<=Sreg;
		endcase
	end
	
	always @(posedge CLOCK)
		case({RESET,ENABLE,C1,C2})
			4'b0100:	begin C1=0;C2=1;end
			4'b0101:	begin C1=1;C2=0;end
			4'b0110:	begin C1=0;C2=0;end
			default:	begin C1=0;C2=0;end
		endcase
	
	
	always @(C1,C2,ENABLE,RESET,Sreg)
		begin
			case(Sreg)
				S0:	case({C1,C2})
						default:	Snext=S1;
					endcase
				S1: case({C1,C2})
						default:	Snext=S2;
					endcase
				S2: case({C1,C2})
						2'b10:		Snext=S1;
						default:	Snext=S3;
					endcase						
				S3: case({C1,C2})
						2'b10:		Snext=S2;
						default:	Snext=S4;
					endcase
				S4: case({C1,C2})
						2'b10:		Snext=S3;
						default:	Snext=S5;
					endcase						
				S5: case({C1,C2})
						2'b10:		Snext=S4;
						default:	Snext=S6;
					endcase						
				S6: case({C1,C2})
						2'b10:		Snext=S5;
						default:	Snext=S7;
					endcase																
				default: case({C1,C2})
						default:	Snext=S7;
					endcase	
			endcase	
		end			
			
	
	
	assign BACK=(C1==1) ? 1:0;
	assign DONE=(Sreg==S7&&ENABLE==1) ? 1:0;
	assign a=(Sreg==S0) ? 1:0;
	assign b=(Sreg==S1) ? 1:0;
	assign c=(Sreg==S2) ? 1:0;
	assign d=(Sreg==S3) ? 1:0;
	assign e=(Sreg==S4) ? 1:0;
	assign f=(Sreg==S5) ? 1:0;
	assign g=(Sreg==S6) ? 1:0;
	
	
endmodule